Generally, when fabricating semiconductor devices, a patterning process of forming patterns on a semiconductor substrate is carried out. In this patterning process, a photoresist is first formed on an etching object layer of the semiconductor substrate. An exposure process for exposing the photoresist of regions to be removed is then performed by irradiating light to the photoresist through a photomask or a reticle. A development process is then performed in order to remove the exposed photoresist. Thus, the photoresist patterns are formed on the etching object layer.
Meanwhile, when fabricating a semiconductor device having a stack structure, it is necessary to correct an alignment state between a layer that was formed in a previous process and a layer that is formed in a current process. To this end, the photoresist patterns for forming real patterns and overlay vernier patterns, which are formed using the same photoresist in order to form overlay verniers, are formed over the etching object layer of the semiconductor substrate. Accordingly, when forming the real patterns by etching the etching object layer using the photoresist patterns, the overlay vernier patterns and the etching object layer are etched to form the overlay verniers. Here, the real pattern and the overlay vernier are formed by the same process, so that the overlay vernier has a vertical sidewall like the real pattern.
Typically, the overlay vernier is formed in a size, which is 10 times larger than that of the real pattern, and is formed independently.
The vertical sidewall of the overlay vernier may cause difficulties in a subsequent process of forming a thin film on the etching object layer over which the real patterns and the overlay verniers are formed. The real pattern has a small pattern size and a narrow gap therebetween. Hence, although the real pattern has a vertical sidewall, the thin film can be formed on the real pattern easily since the thin film is formed in a space between the real patterns. However, an overlay vernier makes it difficult to form the thin film on the sidewalls of the overlay pattern since it has a large pattern size and does not have neighboring patterns.
FIG. 2 is a scanning electron microscope (SEM) photograph of an overlay vernier formed according to the prior art. A side portion of an overlay vernier (indicated by “A”) is formed vertically and has a steep step, which gives damage to a thin film (indicated by “B”) formed on the overlay vernier. In this case, the degree of overlay accuracy when a lower layer is overlapped with an upper layer can be low or impossible to properly overlap the layers in the process.